eForth for STM8S from STMicroelectronics
A 32-Bit Computer for LatticXP2 Brevia Development Kit
eP32 is a 32 bit microprocessor designed to execute FORTH
instructions efficiently. It has 2 stacks, and 27 instructions. Up to 5
instructions are packed in a 32 bit program word. All instructions
including subroutine call and return are executed in a single clock
cycle.
When Lattice announced its Brevia Development Kit at $49, everybody
gets excited. It is by far the cheapest FPGA development system. It
has a FPGA chip LatticeXP2-5E-6TN144C, which has enough logic
cells to implement eP32 CPU core, a UART, and a general purpose
I/O port. It also has enough RAM memory to host eForth operating
system. The nicest thing is that its RAM memory is mirrored in on-chip
flash memory, and the entire eP32 system is contained in a single
XP2-5E chip. All other FPGA's required external components to host a
complete microprocessor system. XP2 is my dreamed SOC chip.
This book contains two major sections, one on hardware design of
eP32 CPU core and a few peripheral devices to form a complete
computer, and one on software design of eForth to run on eP32.
Hardware design is centered on a set of VHDL files, describing
modules in eP32 computer system. Software design is centered on a
set of FORTH files which is a metacompiler constructing a memory
image to initialize RAM memory module in eP32. Generally, I will show
source code on left hand pages, and commentary on the opposing
right hand pages. My perspective is that source code is supreme.
Nothing is more important than source code. If you understand the
complete source code, you understand everything.
Chapters:
1 eP32 Microprocessor
2 Design of eP32
3 eP32 Instructions
4 Implement eP32 on Brevia Kit
5 eP32 Design in VHDL
6 Metacompilation of eP32
All VHDL files in Chapter 5 and all eForth files in Chapter 6 are
included as separated files. Distributed in a 1.8 MB zipped file.
eP32 is a 32 bit microprocessor designed to execute FORTH
instructions efficiently. It has 2 stacks, and 27 instructions. Up to 5
instructions are packed in a 32 bit program word. All instructions
including subroutine call and return are executed in a single clock
cycle.
When Lattice announced its Brevia Development Kit at $49, everybody
gets excited. It is by far the cheapest FPGA development system. It
has a FPGA chip LatticeXP2-5E-6TN144C, which has enough logic
cells to implement eP32 CPU core, a UART, and a general purpose
I/O port. It also has enough RAM memory to host eForth operating
system. The nicest thing is that its RAM memory is mirrored in on-chip
flash memory, and the entire eP32 system is contained in a single
XP2-5E chip. All other FPGA's required external components to host a
complete microprocessor system. XP2 is my dreamed SOC chip.
This book contains two major sections, one on hardware design of
eP32 CPU core and a few peripheral devices to form a complete
computer, and one on software design of eForth to run on eP32.
Hardware design is centered on a set of VHDL files, describing
modules in eP32 computer system. Software design is centered on a
set of FORTH files which is a metacompiler constructing a memory
image to initialize RAM memory module in eP32. Generally, I will show
source code on left hand pages, and commentary on the opposing
right hand pages. My perspective is that source code is supreme.
Nothing is more important than source code. If you understand the
complete source code, you understand everything.
Chapters:
1 eP32 Microprocessor
2 Design of eP32
3 eP32 Instructions
4 Implement eP32 on Brevia Kit
5 eP32 Design in VHDL
6 Metacompilation of eP32
All VHDL files in Chapter 5 and all eForth files in Chapter 6 are
included as separated files. Distributed in a 1.8 MB zipped file.
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