eP Series Microprocessors
This is a series of microprocessor designs scaleable from 8 to 64 bits,
executing the MuP21 instruction set. They were verified on FPGA's and
are available in VHDL source code. The implementations include
development tools like assembler, compiler, interpreter, and simulator.
They are supplied for non-commercial evaluation. Licenses are required
for chip production.
eP8: 16-bit CPU core with 8 bit data bus. It was foundry proven.
eP16: 16-bit CPU core with 16 bit data bus. Verified on Xilinx XC4005XL.
eP24: 24-bit CPU core with 24-bit data bus. Verified on Actel A54SX72A.
eP32: 32-bit CPU core with 32-bit data bus. Verified on Actel ProASIC
APA150, Xilinx Virtex XCV2000E and Altera StratixII EP2S60F672
eP64: 64-bit CPU core with 32-bit data bus. Verified on Xilinx Virtex
XCV2000E.
Offete will provide consulting services to port these implementations to
chips and other FPGA platforms.
This is a series of microprocessor designs scaleable from 8 to 64 bits,
executing the MuP21 instruction set. They were verified on FPGA's and
are available in VHDL source code. The implementations include
development tools like assembler, compiler, interpreter, and simulator.
They are supplied for non-commercial evaluation. Licenses are required
for chip production.
eP8: 16-bit CPU core with 8 bit data bus. It was foundry proven.
eP16: 16-bit CPU core with 16 bit data bus. Verified on Xilinx XC4005XL.
eP24: 24-bit CPU core with 24-bit data bus. Verified on Actel A54SX72A.
eP32: 32-bit CPU core with 32-bit data bus. Verified on Actel ProASIC
APA150, Xilinx Virtex XCV2000E and Altera StratixII EP2S60F672
eP64: 64-bit CPU core with 32-bit data bus. Verified on Xilinx Virtex
XCV2000E.
Offete will provide consulting services to port these implementations to
chips and other FPGA platforms.
eP8 processor on a test board
eP Series Microprocessors
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